00001 /****************************************************************************** 00002 ** Copyright (C) 2007 Pablo Garcia 00003 ** 00004 ** This library is free software; you can redistribute it and/or 00005 ** modify it under the terms of the GNU Lesser General Public 00006 ** License as published by the Free Software Foundation; either 00007 ** version 2.1 of the License, or (at your option) any later version. 00008 00009 ** This library is distributed in the hope that it will be useful, 00010 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 00011 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00012 ** Lesser General Public License for more details. 00013 00014 ** You should have received a copy of the GNU Lesser General Public 00015 ** License along with this library; if not, write to the Free Software 00016 ** Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 00017 ******************************************************************************/ 00018 00019 #include "DataStorage.h" 00020 #include "cpu.h" 00021 #include "TIMotorLIB.h" 00022 00023 #ifdef USE_XINTF 00024 #include GENERATE_FLEX_INC(Xintf.c) 00025 #endif 00026 #ifdef USE_FLASH 00027 #include GENERATE_FLEX_INC(SysCtrl.c) 00028 #endif 00029 00030 00031 Uint16 dataStorageBuffer[BUFSIZE]; // data storage buffer 00032 Uint16* dataPtr; // write pointer 00033 Uint16* begin; // buffer begin 00034 Uint16* end; // buffer end 00035 Uint32* actualPos; // actualPos 00036 Uint16 clearDataStorage; // clear memory 00037 STORAGEMODE storageMode; // storage mode 00038 00039 // memory map 00040 00041 // data storage in external memory 00042 #ifdef USE_XINTF 00043 #pragma DATA_SECTION(dataStorageBuffer,"ZONE7ST"); 00044 #endif 00045 00046 // data storage in flash 00047 #ifdef USE_FLASH 00048 #pragma DATA_SECTION(dataStorageBuffer,"FLASHST"); 00049 #endif 00050 00051 volatile int flashlock=0; 00052 00053 00054 //void InitXintf16Gpio(void); 00055 void InitXintfTIMotorLIB(void); 00056 00057 /*----------------------------------------------------------------------------- 00058 Functions 00059 ------------------------------------------------------------------------------*/ 00060 00061 00074 /*void InitXintf16Gpio(void) 00075 { 00076 EALLOW; 00077 // data bus 00078 GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 00079 GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 00080 GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 00081 GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 00082 GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 00083 GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 00084 GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 00085 GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 00086 GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 00087 GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 00088 GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 00089 GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 00090 GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 00091 GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 00092 GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 00093 GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 00094 00095 // address bus 00096 GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n 00097 GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 00098 GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 00099 GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 00100 GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 00101 GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 00102 GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 00103 GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 00104 GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 00105 GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 00106 GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 00107 GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 00108 GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 00109 GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 00110 GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 00111 GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 00112 GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 00113 00114 GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY 00115 GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW 00116 GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 00117 00118 // GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 00119 // chip select zone 7 00120 GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 00121 // GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 00122 EDIS; 00123 }*/ 00124 00125 // ---------------------------------------------------------------------------- 00126 00127 00132 /*void InitXintf(void) 00133 { 00134 // This shows how to write to the XINTF registers. The 00135 // values used here are the default state after reset. 00136 // Different hardware will require a different configuration. 00137 00138 // For an example of an XINTF configuration used with the 00139 // F28335 eZdsp, refer to the examples/run_from_xintf . 00140 00141 // Any changes to XINTF timing should only be made by code 00142 // running outside of the XINTF. 00143 00144 // Make sure the XINTF clock is enabled 00145 EALLOW; 00146 SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; 00147 EDIS; 00148 // All Zones--------------------------------- 00149 // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT 00150 00151 EALLOW; 00152 XintfRegs.XINTCNF2.bit.XTIMCLK = 1; 00153 // No write buffering 00154 XintfRegs.XINTCNF2.bit.WRBUFF = 0; 00155 // XCLKOUT is enabled 00156 XintfRegs.XINTCNF2.bit.CLKOFF = 0; 00157 // XCLKOUT = XTIMCLK/2 00158 XintfRegs.XINTCNF2.bit.CLKMODE = 1; 00159 00160 00161 // Zone 7------------------------------------ 00162 // When using ready, ACTIVE must be 1 or greater 00163 // Lead must always be 1 or greater 00164 // Zone write timing 00165 XintfRegs.XTIMING7.bit.XWRLEAD = 3; 00166 XintfRegs.XTIMING7.bit.XWRACTIVE = 7; 00167 XintfRegs.XTIMING7.bit.XWRTRAIL = 3; 00168 // Zone read timing 00169 XintfRegs.XTIMING7.bit.XRDLEAD = 3; 00170 XintfRegs.XTIMING7.bit.XRDACTIVE = 7; 00171 XintfRegs.XTIMING7.bit.XRDTRAIL = 3; 00172 00173 // double all Zone read/write lead/active/trail timing 00174 XintfRegs.XTIMING7.bit.X2TIMING = 1; 00175 00176 // Zone will sample XREADY signal 00177 XintfRegs.XTIMING7.bit.USEREADY = 1; 00178 XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous 00179 00180 // Size must be either: 00181 // 0,1 = x32 or 00182 // 1,1 = x16 other values are reserved 00183 XintfRegs.XTIMING7.bit.XSIZE = 3; 00184 00185 // Bank switching 00186 // Assume Zone 7 is slow, so add additional BCYC cycles 00187 // when ever switching from Zone 7 to another Zone. 00188 // This will help avoid bus contention. 00189 XintfRegs.XBANK.bit.BANK = 7; 00190 XintfRegs.XBANK.bit.BCYC = 7; 00191 EDIS; 00192 //Force a pipeline flush to ensure that the write to 00193 //the last register configured occurs before returning. 00194 00195 InitXintf16Gpio(); 00196 00197 asm(" RPT #7 || NOP"); 00198 00199 }*/ 00200 00201 // ---------------------------------------------------------------------------- 00202 00203 void InitXintfTIMotorLIB(void) 00204 { 00205 // Make sure the XINTF clock is enabled 00206 EALLOW; 00207 SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; 00208 EDIS; 00209 InitXintf(); 00210 } 00211 00212 // ---------------------------------------------------------------------------- 00213 00216 void InitFlash(void) 00217 { 00218 EALLOW; 00219 //Enable Flash Pipeline mode to improve performance 00220 //of code executed from Flash. 00221 FlashRegs.FOPT.bit.ENPIPE = 1; 00222 00223 // CAUTION 00224 //Minimum waitstates required for the flash operating 00225 //at a given CPU rate must be characterized by TI. 00226 //Refer to the datasheet for the latest information. 00227 #if CPU_FRQ_150MHZ 00228 //Set the Paged Waitstate for the Flash 00229 FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; 00230 00231 //Set the Random Waitstate for the Flash 00232 FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; 00233 00234 //Set the Waitstate for the OTP 00235 FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; 00236 #endif 00237 00238 #if CPU_FRQ_100MHZ 00239 //Set the Paged Waitstate for the Flash 00240 FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; 00241 00242 //Set the Random Waitstate for the Flash 00243 FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; 00244 00245 //Set the Waitstate for the OTP 00246 FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; 00247 #endif 00248 // CAUTION 00249 //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED 00250 FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; 00251 FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; 00252 EDIS; 00253 00254 //Force a pipeline flush to ensure that the write to 00255 //the last register configured occurs before returning. 00256 00257 asm(" RPT #7 || NOP"); 00258 } 00259 00260 // ---------------------------------------------------------------------------- 00261 00262 #define STATUS_FAIL 0 00263 #define STATUS_SUCCESS 1 00264 00267 Uint16 CsmUnlock() 00268 { 00269 volatile Uint16 temp; 00270 00271 // Load the key registers with the current password. The 0xFFFF's are dummy 00272 // passwords. User should replace them with the correct password for the DSP. 00273 00274 EALLOW; 00275 CsmRegs.KEY0 = 0xFFFF; 00276 CsmRegs.KEY1 = 0xFFFF; 00277 CsmRegs.KEY2 = 0xFFFF; 00278 CsmRegs.KEY3 = 0xFFFF; 00279 CsmRegs.KEY4 = 0xFFFF; 00280 CsmRegs.KEY5 = 0xFFFF; 00281 CsmRegs.KEY6 = 0xFFFF; 00282 CsmRegs.KEY7 = 0xFFFF; 00283 EDIS; 00284 00285 // Perform a dummy read of the password locations 00286 // if they match the key values, the CSM will unlock 00287 00288 temp = CsmPwl.PSWD0; 00289 temp = CsmPwl.PSWD1; 00290 temp = CsmPwl.PSWD2; 00291 temp = CsmPwl.PSWD3; 00292 temp = CsmPwl.PSWD4; 00293 temp = CsmPwl.PSWD5; 00294 temp = CsmPwl.PSWD6; 00295 temp = CsmPwl.PSWD7; 00296 00297 // If the CSM unlocked, return succes, otherwise return 00298 // failure. 00299 if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS; 00300 else return STATUS_FAIL; 00301 00302 } 00303 00304 // ---------------------------------------------------------------------------- 00305 00306 void InitDataStorageBuffer(STORAGEMODE mode) 00307 { 00308 // init hardware resources 00309 #ifdef USE_XINTF 00310 InitXintfTIMotorLIB(); 00311 #endif 00312 #ifdef USE_FLASH 00313 InitFlash(); 00314 //flashlock = CsmUnlock(); 00315 #endif 00316 // init software resources 00317 begin=dataStorageBuffer; 00318 end=dataStorageBuffer+BUFSIZE-2; 00319 actualPos = (Uint32*)end; 00320 for(dataPtr=begin;dataPtr<=end;dataPtr++) 00321 *dataPtr=0; 00322 dataPtr=begin; 00323 clearDataStorage=0; 00324 storageMode=mode; 00325 } 00326 00327 //----------------------------------------------------------------------------- 00328 // End Of File 00329 //----------------------------------------------------------------------------- 00330