00001 /****************************************************************************** 00002 ** Copyright (C) 2010 00003 ** Silvia Izquierdo Rosas <silvia.izquierdo.rosas@gmail.com> 00004 ** Christian Blanco Charro <khristian996@gmail.com> 00005 ** 00006 ** This library is free software; you can redistribute it and/or 00007 ** modify it under the terms of the GNU Lesser General Public 00008 ** License as published by the Free Software Foundation; either 00009 ** version 2.1 of the License, or (at your option) any later version. 00010 00011 ** This library is distributed in the hope that it will be useful, 00012 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 00013 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00014 ** Lesser General Public License for more details. 00015 00016 ** You should have received a copy of the GNU Lesser General Public 00017 ** License along with this library; if not, write to the Free Software 00018 ** Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 00019 ******************************************************************************/ 00020 00021 // ---------------------------------------------------------------------------- 00022 // Includes 00023 // ---------------------------------------------------------------------------- 00024 #include "TIMotorLIB.h" 00025 #include "DataStorage.h" 00026 #include "sci.h" 00027 00028 // ---------------------------------------------------------------------------- 00029 00030 void ConfigureSCI(void(*interruptFCN)(void), 00031 SCI_PORT sciPort, Uint32 speed, SCI_STOPBIT stopBit , SCI_PARITY parity, 00032 SCI_PARITY_ENABLE sciParityEnable, Uint16 nbit) 00033 00034 { 00035 volatile struct SCI_REGS* sciRegs; 00036 Uint16 BRB; 00037 if(sciPort == SCIA) { 00038 sciRegs = &SciaRegs; 00039 EALLOW; 00040 SysCtrlRegs.PCLKCR0.bit.SCIAENCLK = 1; // Clocks were turned on to the SCIA peripheral 00041 EDIS; 00042 } 00043 else if(sciPort == SCIB){ 00044 sciRegs = &ScibRegs; 00045 EALLOW; 00046 SysCtrlRegs.PCLKCR0.bit.SCIBENCLK = 1; // Clocks were turned on to the SCIB peripheral 00047 EDIS; 00048 } 00049 InitSCIGpio(sciPort); 00050 SciFifoInit(sciRegs); // Initialize the SCI FIFO 00051 00052 00053 if(interruptFCN != 0) { 00054 if(sciPort == SCIA){ 00055 EALLOW; 00056 PieVectTable.SCIRXINTA = interruptFCN; 00057 EDIS; 00058 PieCtrlRegs.PIEIER9.bit.INTx1=1; // PIE Group 9, int1 SCIRXINTA 00059 IER |= M_INT9; // Enable CPU INT 00060 } 00061 else if(sciPort == SCIB){ 00062 EALLOW; 00063 PieVectTable.SCIRXINTB = interruptFCN; 00064 EDIS; 00065 PieCtrlRegs.PIEIER9.bit.INTx3=1; // PIE Group 9, int3 SCIRXINTB 00066 IER |= M_INT9; // Enable CPU INT 00067 } 00068 EINT; 00069 } 00070 // SCICCR 00071 sciRegs->SCICCR.bit.STOPBITS = stopBit; 00072 sciRegs->SCICCR.bit.PARITY = parity; 00073 sciRegs->SCICCR.bit.PARITYENA = sciParityEnable; 00074 sciRegs->SCICCR.bit.LOOPBKENA = 0; // disable loopback 00075 sciRegs->SCICCR.bit.ADDRIDLE_MODE = 0; //Idle line mode protocol 00076 sciRegs->SCICCR.bit.SCICHAR = nbit-1; 00077 // SCICTL1 00078 sciRegs->SCICTL1.bit.RXERRINTENA = 0; //Receive error interrupt disabled 00079 sciRegs->SCICTL1.bit.SWRESET = 0; //Initializes SCI state machines and operating flags to the reset condition 00080 sciRegs->SCICTL1.bit.TXWAKE = 0; //Transmit feature is not selected 00081 sciRegs->SCICTL1.bit.SLEEP = 0; //Sleep mode disabled 00082 sciRegs->SCICTL1.bit.TXENA = 1; //Transmitter enabled 00083 sciRegs->SCICTL1.bit.RXENA = 1; //Send received character to SCIRXEMU and SCIRXBUF 00084 // SCICTL2 00085 sciRegs->SCICTL2.bit.RXBKINTENA =1; // Enable RXRDY/BRKDT interrupt 00086 00087 // Port speed configuration: spru051b.pdf --> pag. 28 00088 // if BRB = 0 --> Baud rate = LSPCLK/16 00089 BRB = (Uint32)(_IQtoF(LspCLKInMhz())*1000000)/(speed << 3) - 1; 00090 SciaRegs.SCIHBAUD = (BRB & 0xFF00) >> 8; 00091 SciaRegs.SCILBAUD = (BRB & 0x00FF); 00092 00093 sciRegs->SCIFFRX.bit.RXFIFORESET = 1; //Re-enable receive FIFO operation 00094 sciRegs->SCIFFTX.bit.TXFIFOXRESET = 1; //Re-enable transmit FIFO operation 00095 sciRegs->SCICTL1.bit.SWRESET = 1; //After a system reset, re-enable the SCI by writing a 1 to this bit 00096 00097 } 00098 00099 // ---------------------------------------------------------------------------- 00100 00101 void SciFifoInit(volatile struct SCI_REGS* sciRegs) 00102 { 00103 //SCIFFTX = 0xE040 spru051b.pdf --> pag. 34 00104 sciRegs->SCIFFTX.bit.SCIRST = 1; //SCI can transmit or receive 00105 sciRegs->SCIFFTX.bit.SCIFFENA = 1; //SCI FIFO enhancements enabled 00106 sciRegs->SCIFFTX.bit.TXFIFOXRESET = 0; //Re-enable transmit FIFO operation 00107 sciRegs->SCIFFTX.bit.TXFFINTCLR = 1; //To clear TRFFINT flag in bit 7 --NO CAMBIA-- 00108 sciRegs->SCIFFTX.bit.TXFFIENA = 0; //Interrupt based on TXFFIVL disabled 00109 sciRegs->SCIFFTX.bit.TXFFIL = 0; //Transmit FIFO level bits 00110 00111 //SCIFFRX = 0x0021 spru051b.pdf --> pag. 35 00112 sciRegs->SCIFFRX.bit.RXFFOVRCLR = 1; //Has no effect on RXFFOVF, bit reads back a zero 00113 sciRegs->SCIFFRX.bit.RXFIFORESET = 0; //Reset the FIFO pointer to zero, and hold in reset 00114 sciRegs->SCIFFRX.bit.RXFFINTCLR = 1; //Has no effect on RXFFOVF, bit reads back a zero 00115 sciRegs->SCIFFRX.bit.RXFFIENA = 1; //RX FIFO interrupt based on RXFFIVL match will be enabled 00116 sciRegs->SCIFFRX.bit.RXFFIL = 1; //Receive FIFO interrupt level bits 00117 00118 00119 //SCIFFCT = 0x0; spru051b.pdf --> pag. 36 00120 sciRegs->SCIFFCT.bit.ABDCLR = 0; //Has no effect on ABD flag bit 00121 sciRegs->SCIFFCT.bit.CDC = 0; //Disables auto-baud alignment 00122 sciRegs->SCIFFCT.bit.FFTXDLY = 0; //FIFO transfer delay 00123 } 00124 00125 // ---------------------------------------------------------------------------- 00126 00127 void InitSCIGpio(SCI_PORT sciPort) 00128 { 00129 // TODO: GPIO port selection depends on the particular hardware --> configurable 00130 if(sciPort == SCIA) { // RX: 28/36, TX: 29,35 00131 EALLOW; 00132 GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) 00133 GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) 00134 GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) 00135 GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation 00136 GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation 00137 EDIS; 00138 00139 /*EALLOW; 00140 GpioCtrlRegs.GPBPUD.bit.GPIO35 = 0; // Enable pull-up for GPIO35 (SCITXDA) 00141 GpioCtrlRegs.GPBPUD.bit.GPIO36 = 0; // Enable pull-up for GPIO29 (SCIRXDA) 00142 GpioCtrlRegs.GPBQSEL1.bit.GPIO36 = 3; // Asynch input GPIO36 (SCIRXDA) 00143 GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 1; // Configure GPIO35 for SCITXDA operation 00144 GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 1; // Configure GPIO36 for SCIRXDA operation 00145 EDIS;*/ 00146 00147 } 00148 else if(sciPort == SCIB) { // RX: 11/15/19/23, TX: 9/14/18/22 00149 EALLOW; 00150 // TODO: 00151 EDIS; 00152 } 00153 } 00154 00155 void EnableSCITXInterrupt(SCI_PORT sciPort, void(*interruptFCN)(void), unsigned char fifoLevel) 00156 { 00157 volatile struct SCI_REGS* sciRegs; 00158 if(sciPort == SCIA){ 00159 sciRegs = &SciaRegs; 00160 EALLOW; 00161 PieVectTable.SCITXINTA = interruptFCN; 00162 EDIS; 00163 PieCtrlRegs.PIEIER9.bit.INTx2=1; // PIE Group 9, int2 SCITXINTA 00164 IER |= M_INT9; // Enable CPU INT 00165 } 00166 else if(sciPort == SCIB){ 00167 sciRegs = &ScibRegs; 00168 EALLOW; 00169 PieVectTable.SCITXINTB = interruptFCN; 00170 EDIS; 00171 PieCtrlRegs.PIEIER9.bit.INTx4=1; // PIE Group 9, int4 SCITXINTB 00172 IER |= M_INT9; // Enable CPU INT 00173 } 00174 EINT; 00175 00176 sciRegs->SCIFFTX.bit.TXFFIENA = 1; //Interrupt based on TXFFIVL enabled 00177 sciRegs->SCIFFTX.bit.TXFFIL = 16-fifoLevel; //Transmit FIFO level bits 00178 sciRegs->SCIFFTX.bit.TXFIFOXRESET = 1; //Re-enable transmit FIFO operation 00179 sciRegs->SCICTL1.bit.SWRESET = 1; //After a system reset, re-enable the SCI by writing a 1 to this bit 00180 } 00181 00182 // ---------------------------------------------------------------------------- 00183 00184 void DisableSCITXInterrupt(SCI_PORT sciPort) 00185 { 00186 volatile struct SCI_REGS* sciRegs; 00187 if(sciPort == SCIA){ 00188 sciRegs = &SciaRegs; 00189 } 00190 else if(sciPort == SCIB){ 00191 sciRegs = &ScibRegs; 00192 } 00193 sciRegs->SCIFFTX.bit.TXFFIENA = 0; //Interrupt based on TXFFIVL disabled 00194 sciRegs->SCIFFTX.bit.TXFFIL = 0; //Transmit FIFO level bits 00195 } 00196 00197 // ---------------------------------------------------------------------------- 00198 00199 /* 00200 // TODO: Pablo: SerĂa mejor almacenar el indice de leidas en la unidad y que el 00201 // usuario se despreocupara de ellas 00202 int AddVar2List(char *name,void *pointer,int readedInx,struct VAR_DESC *variables) 00203 { 00204 int i; 00205 00206 if(readedInx<TAM_LISTA_VAR){ 00207 for(i=0;i<TAM_NOMBRE_VAR;i++) 00208 *variables[readedInx].VarName=name[i]; 00209 00210 variables[readedInx].PVar=pointer; 00211 return 1; 00212 } 00213 return 0; 00214 } 00215 00216 // ---------------------------------------------------------------------------- 00217 00218 void ResetVector(Uint16* begin, Uint16* end) 00219 { 00220 Uint16* i; 00221 00222 for(i=begin;i<end;i++) 00223 *i=0; 00224 00225 } 00226 00227 // ---------------------------------------------------------------------------- 00228 */ 00229 00230 //----------------------------------------------------------------------------- 00231 // End Of File 00232 //-----------------------------------------------------------------------------