00001 /****************************************************************************** 00002 ** Copyright (C) 2007 Pablo Garcia 00003 ** 00004 ** This library is free software; you can redistribute it and/or 00005 ** modify it under the terms of the GNU Lesser General Public 00006 ** License as published by the Free Software Foundation; either 00007 ** version 2.1 of the License, or (at your option) any later version. 00008 00009 ** This library is distributed in the hope that it will be useful, 00010 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 00011 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00012 ** Lesser General Public License for more details. 00013 00014 ** You should have received a copy of the GNU Lesser General Public 00015 ** License along with this library; if not, write to the Free Software 00016 ** Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 00017 ******************************************************************************/ 00018 00019 #include "DataStorage.h" 00020 #include "cpu.h" 00021 #include "TIMotorLIB.h" 00022 00023 00024 #ifdef USE_XINTF 00025 #include GENERATE_FLEX_INC(Xintf.c) 00026 #endif 00027 #ifdef USE_FLASH 00028 #include GENERATE_FLEX_INC(SysCtrl.c) 00029 #endif 00030 00031 // use DataStorage only when whanted 00032 #ifdef MEM_STORAGE_DEFINED 00033 00034 Uint16 dataStorageBuffer[BUFSIZE]; // data storage buffer 00035 Uint16* dataPtr; // write pointer 00036 Uint16* begin; // buffer begin 00037 Uint16* end; // buffer end 00038 Uint32* actualPos; // actualPos 00039 Uint16 clearDataStorage; // clear memory 00040 STORAGEMODE storageMode; // storage mode 00041 00042 // memory map 00043 00044 // data storage in external memory 00045 #ifdef USE_XINTF 00046 #pragma DATA_SECTION(dataStorageBuffer,"ZONE7ST"); 00047 #endif 00048 00049 // data storage in flash 00050 #ifdef USE_FLASH 00051 #pragma DATA_SECTION(dataStorageBuffer,"FLASHST"); 00052 #endif 00053 00054 volatile int flashlock=0; 00055 00056 00057 //void InitXintf16Gpio(void); 00058 void InitXintfTIMotorLIB(void); 00059 00060 /*----------------------------------------------------------------------------- 00061 Functions 00062 ------------------------------------------------------------------------------*/ 00063 00064 00077 /*void InitXintf16Gpio(void) 00078 { 00079 EALLOW; 00080 // data bus 00081 GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 00082 GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 00083 GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 00084 GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 00085 GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 00086 GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 00087 GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 00088 GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 00089 GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 00090 GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 00091 GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 00092 GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 00093 GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 00094 GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 00095 GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 00096 GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 00097 00098 // address bus 00099 GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n 00100 GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 00101 GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 00102 GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 00103 GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 00104 GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 00105 GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 00106 GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 00107 GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 00108 GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 00109 GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 00110 GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 00111 GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 00112 GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 00113 GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 00114 GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 00115 GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 00116 00117 GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY 00118 GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW 00119 GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 00120 00121 // GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 00122 // chip select zone 7 00123 GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 00124 // GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 00125 EDIS; 00126 }*/ 00127 00128 // ---------------------------------------------------------------------------- 00129 00130 00135 /*void InitXintf(void) 00136 { 00137 // This shows how to write to the XINTF registers. The 00138 // values used here are the default state after reset. 00139 // Different hardware will require a different configuration. 00140 00141 // For an example of an XINTF configuration used with the 00142 // F28335 eZdsp, refer to the examples/run_from_xintf . 00143 00144 // Any changes to XINTF timing should only be made by code 00145 // running outside of the XINTF. 00146 00147 // Make sure the XINTF clock is enabled 00148 EALLOW; 00149 SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; 00150 EDIS; 00151 // All Zones--------------------------------- 00152 // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT 00153 00154 EALLOW; 00155 XintfRegs.XINTCNF2.bit.XTIMCLK = 1; 00156 // No write buffering 00157 XintfRegs.XINTCNF2.bit.WRBUFF = 0; 00158 // XCLKOUT is enabled 00159 XintfRegs.XINTCNF2.bit.CLKOFF = 0; 00160 // XCLKOUT = XTIMCLK/2 00161 XintfRegs.XINTCNF2.bit.CLKMODE = 1; 00162 00163 00164 // Zone 7------------------------------------ 00165 // When using ready, ACTIVE must be 1 or greater 00166 // Lead must always be 1 or greater 00167 // Zone write timing 00168 XintfRegs.XTIMING7.bit.XWRLEAD = 3; 00169 XintfRegs.XTIMING7.bit.XWRACTIVE = 7; 00170 XintfRegs.XTIMING7.bit.XWRTRAIL = 3; 00171 // Zone read timing 00172 XintfRegs.XTIMING7.bit.XRDLEAD = 3; 00173 XintfRegs.XTIMING7.bit.XRDACTIVE = 7; 00174 XintfRegs.XTIMING7.bit.XRDTRAIL = 3; 00175 00176 // double all Zone read/write lead/active/trail timing 00177 XintfRegs.XTIMING7.bit.X2TIMING = 1; 00178 00179 // Zone will sample XREADY signal 00180 XintfRegs.XTIMING7.bit.USEREADY = 1; 00181 XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous 00182 00183 // Size must be either: 00184 // 0,1 = x32 or 00185 // 1,1 = x16 other values are reserved 00186 XintfRegs.XTIMING7.bit.XSIZE = 3; 00187 00188 // Bank switching 00189 // Assume Zone 7 is slow, so add additional BCYC cycles 00190 // when ever switching from Zone 7 to another Zone. 00191 // This will help avoid bus contention. 00192 XintfRegs.XBANK.bit.BANK = 7; 00193 XintfRegs.XBANK.bit.BCYC = 7; 00194 EDIS; 00195 //Force a pipeline flush to ensure that the write to 00196 //the last register configured occurs before returning. 00197 00198 InitXintf16Gpio(); 00199 00200 asm(" RPT #7 || NOP"); 00201 00202 }*/ 00203 00204 // ---------------------------------------------------------------------------- 00205 00206 void InitXintfTIMotorLIB(void) 00207 { 00208 // Make sure the XINTF clock is enabled 00209 EALLOW; 00210 SysCtrlRegs.PCLKCR3.bit.XINTFENCLK = 1; 00211 EDIS; 00212 InitXintf(); 00213 } 00214 00215 // ---------------------------------------------------------------------------- 00216 00219 void InitFlash(void) 00220 { 00221 EALLOW; 00222 //Enable Flash Pipeline mode to improve performance 00223 //of code executed from Flash. 00224 FlashRegs.FOPT.bit.ENPIPE = 1; 00225 00226 // CAUTION 00227 //Minimum waitstates required for the flash operating 00228 //at a given CPU rate must be characterized by TI. 00229 //Refer to the datasheet for the latest information. 00230 #if CPU_FRQ_150MHZ 00231 //Set the Paged Waitstate for the Flash 00232 FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; 00233 00234 //Set the Random Waitstate for the Flash 00235 FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; 00236 00237 //Set the Waitstate for the OTP 00238 FlashRegs.FOTPWAIT.bit.OTPWAIT = 8; 00239 #endif 00240 00241 #if CPU_FRQ_100MHZ 00242 //Set the Paged Waitstate for the Flash 00243 FlashRegs.FBANKWAIT.bit.PAGEWAIT = 3; 00244 00245 //Set the Random Waitstate for the Flash 00246 FlashRegs.FBANKWAIT.bit.RANDWAIT = 3; 00247 00248 //Set the Waitstate for the OTP 00249 FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; 00250 #endif 00251 // CAUTION 00252 //ONLY THE DEFAULT VALUE FOR THESE 2 REGISTERS SHOULD BE USED 00253 FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; 00254 FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; 00255 EDIS; 00256 00257 //Force a pipeline flush to ensure that the write to 00258 //the last register configured occurs before returning. 00259 00260 asm(" RPT #7 || NOP"); 00261 } 00262 00263 // ---------------------------------------------------------------------------- 00264 00265 #define STATUS_FAIL 0 00266 #define STATUS_SUCCESS 1 00267 00270 Uint16 CsmUnlock() 00271 { 00272 volatile Uint16 temp; 00273 00274 // Load the key registers with the current password. The 0xFFFF's are dummy 00275 // passwords. User should replace them with the correct password for the DSP. 00276 00277 EALLOW; 00278 CsmRegs.KEY0 = 0xFFFF; 00279 CsmRegs.KEY1 = 0xFFFF; 00280 CsmRegs.KEY2 = 0xFFFF; 00281 CsmRegs.KEY3 = 0xFFFF; 00282 CsmRegs.KEY4 = 0xFFFF; 00283 CsmRegs.KEY5 = 0xFFFF; 00284 CsmRegs.KEY6 = 0xFFFF; 00285 CsmRegs.KEY7 = 0xFFFF; 00286 EDIS; 00287 00288 // Perform a dummy read of the password locations 00289 // if they match the key values, the CSM will unlock 00290 00291 temp = CsmPwl.PSWD0; 00292 temp = CsmPwl.PSWD1; 00293 temp = CsmPwl.PSWD2; 00294 temp = CsmPwl.PSWD3; 00295 temp = CsmPwl.PSWD4; 00296 temp = CsmPwl.PSWD5; 00297 temp = CsmPwl.PSWD6; 00298 temp = CsmPwl.PSWD7; 00299 00300 // If the CSM unlocked, return succes, otherwise return 00301 // failure. 00302 if (CsmRegs.CSMSCR.bit.SECURE == 0) return STATUS_SUCCESS; 00303 else return STATUS_FAIL; 00304 00305 } 00306 00307 // ---------------------------------------------------------------------------- 00308 00309 void InitDataStorageBuffer(STORAGEMODE mode) 00310 { 00311 // init hardware resources 00312 #ifdef USE_XINTF 00313 InitXintfTIMotorLIB(); 00314 #endif 00315 #ifdef USE_FLASH 00316 InitFlash(); 00317 //flashlock = CsmUnlock(); 00318 #endif 00319 // init software resources 00320 begin=dataStorageBuffer; 00321 end=dataStorageBuffer+BUFSIZE-2; 00322 actualPos = (Uint32*)end; 00323 for(dataPtr=begin;dataPtr<=end;dataPtr++) 00324 *dataPtr=0; 00325 dataPtr=begin; 00326 clearDataStorage=0; 00327 storageMode=mode; 00328 } 00329 00330 #endif // #ifndef NO_DATA_STORAGE 00331 00332 //----------------------------------------------------------------------------- 00333 // End Of File 00334 //----------------------------------------------------------------------------- 00335