00001 /****************************************************************************** 00002 ** Copyright (C) 2010 00003 ** Pablo García Fernández <pgarcia@isa.uniovi.es> 00004 ** 00005 ** This library is free software; you can redistribute it and/or 00006 ** modify it under the terms of the GNU Lesser General Public 00007 ** License as published by the Free Software Foundation; either 00008 ** version 2.1 of the License, or (at your option) any later version. 00009 00010 ** This library is distributed in the hope that it will be useful, 00011 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 00013 ** Lesser General Public License for more details. 00014 00015 ** You should have received a copy of the GNU Lesser General Public 00016 ** License along with this library; if not, write to the Free Software 00017 ** Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 00018 ******************************************************************************/ 00019 00020 // ---------------------------------------------------------------------------- 00021 // Includes 00022 // ---------------------------------------------------------------------------- 00023 #include "TIMotorLIB.h" 00024 #include "spi.h" 00025 00026 void SpiFifoInit(void); 00027 00028 void ConfigureSPIA(void(*interruptRX)(void), 00029 void(*interruptTX)(void), SPINMC networkModeControl, 00030 SPILBK spiLoopBack, Uint32 speed, Uint16 SPIcharLength, Uint16 txFIFO, Uint16 rxFIFO) 00031 { 00032 Uint16 spiIntEna=0; 00033 Uint16 brr; 00034 Uint32 lspCLK; 00035 EALLOW; 00036 SysCtrlRegs.PCLKCR0.bit.SPIAENCLK = 1; // Clocks were turned on to the SPIA peripheral 00037 EDIS; 00038 InitSpiaGpio(); 00039 //SpiFifoInit(); 00040 // Initialize SPI FIFO registers 00041 SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI 00042 SpiaRegs.SPICCR.bit.SPILBK = spiLoopBack; // SPI lookback 00043 SpiaRegs.SPICCR.bit.SPICHAR = SPIcharLength-1; 00044 // Operation Control Register 00045 SpiaRegs.SPICTL.bit.MASTER_SLAVE = networkModeControl; 00046 SpiaRegs.SPICTL.bit.TALK = 1; 00047 SpiaRegs.SPISTS.all=0x0000; // reset status register 00048 SpiaRegs.SPIFFTX.bit.SPIRST = 1; // reset transmit/receive chanels 00049 SpiaRegs.SPIFFTX.bit.SPIFFENA = 1; // enhancements enabled 00050 SpiaRegs.SPIFFTX.bit.TXFFIL = txFIFO; // Transmission FIFO level 00051 SpiaRegs.SPIFFRX.bit.RXFFIL = rxFIFO; // Receive FIFO level 00052 SpiaRegs.SPIFFRX.bit.RXFFOVFCLR = 1; // Clear RX overflow flag 00053 SpiaRegs.SPIFFCT.all=0x00; // FIFO transmit delay 00054 SpiaRegs.SPIPRI.all=0x0010; 00055 SpiaRegs.SPIPRI.bit.FREE = 1; // Set so breakpoints don't disturb xmission 00056 EALLOW; // This is needed to write to EALLOW protected registers 00057 if(interruptRX != 0) { 00058 spiIntEna=1; 00059 SpiaRegs.SPIFFRX.bit.RXFFIENA=1; 00060 PieVectTable.SPIRXINTA = interruptRX; 00061 PieCtrlRegs.PIEIER6.bit.INTx1=1; // Enable PIE Group 6, INT 1 00062 } 00063 if(interruptTX != 0) { 00064 spiIntEna=1; 00065 SpiaRegs.SPIFFTX.bit.TXFFIENA=1; 00066 PieVectTable.SPITXINTA = interruptTX; 00067 PieCtrlRegs.PIEIER6.bit.INTx2=1; // Enable PIE Group 6, INT 2 00068 } 00069 if(spiIntEna){ 00070 SpiaRegs.SPICTL.bit.SPIINTENA = 1; 00071 IER |= M_INT6; // Enable CPU INT 00072 } 00073 EDIS; // This is needed to disable write to EALLOW protected registers 00074 00075 00076 // Port speed configuration: sprueu3a.pdf --> pag. 18 00077 // if BRR = 0, 1, 2 --> Baud rate = LSPCLK/4 00078 lspCLK = (Uint32)(_IQtoF(LspCLKInMhz())); 00079 if(speed >= (lspCLK>>2)) 00080 brr = 0; 00081 else 00082 brr = lspCLK/speed - 1; 00083 //brr = 9; 00084 SpiaRegs.SPIBRR = brr; 00085 00086 StartTransmission(); 00087 } 00088 00089 // ---------------------------------------------------------------------------- 00090 00091 void InitSpiaGpio(void) 00092 { 00093 EALLOW; 00094 // Enable internal pull-up for the selected pins 00095 GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) 00096 GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) 00097 GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) 00098 GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) 00099 00100 /*GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) 00101 GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) 00102 GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) 00103 GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA) 00104 */ 00105 // Set qualification for selected pins to asynch only 00106 GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) 00107 GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) 00108 GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) 00109 GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) 00110 00111 /*GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) 00112 GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) 00113 GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) 00114 GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) 00115 */ 00116 // Configure SPI-A pins using GPIO regs* 00117 GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA 00118 GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA 00119 GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA 00120 GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA 00121 00122 /*GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA 00123 GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA 00124 GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA 00125 GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA 00126 */ 00127 EDIS; 00128 } 00129 00130 // ---------------------------------------------------------------------------- 00131 00132 void SpiFifoInit(void) 00133 { 00134 // Initialize SPI FIFO registers 00135 SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI 00136 00137 SpiaRegs.SPICCR.all=0x001F; //16-bit character, Loopback mode 00138 SpiaRegs.SPICTL.all=0x0017; //Interrupt enabled, Master/Slave XMIT enabled 00139 SpiaRegs.SPISTS.all=0x0000; 00140 SpiaRegs.SPIBRR=0x0063; // Baud rate 00141 SpiaRegs.SPIFFTX.all=0xC028; // Enable FIFO's, set TX FIFO level to 8 00142 SpiaRegs.SPIFFRX.all=0x0028; // Set RX FIFO level to 8 00143 SpiaRegs.SPIFFCT.all=0x00; 00144 SpiaRegs.SPIPRI.all=0x0010; 00145 00146 SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI 00147 00148 SpiaRegs.SPIFFTX.bit.TXFIFO=1; 00149 SpiaRegs.SPIFFRX.bit.RXFIFORESET=1; 00150 } 00151 00152 // ---------------------------------------------------------------------------- 00153 00154 //----------------------------------------------------------------------------- 00155 // End Of File 00156 //-----------------------------------------------------------------------------