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00024 #include "qep.h"
00025 #include "cpu.h"
00026
00027
00028
00029
00030
00031
00032 volatile struct QEP qep1;
00033 volatile struct QEP qep2;
00034
00035
00036
00037
00038 void InitQEP1(void(*interruptFCN)(void), Uint16 qep_us, PCRM pcrm,
00039 Uint16 lines, Uint16 polePairs);
00040 void InitQEP2(void(*interruptFCN)(void), Uint16 qep_us, PCRM pcrm,
00041 Uint16 lines, Uint16 polePairs);
00042 static inline void StoreQEPConf(volatile struct QEP* qep,
00043 volatile struct EQEP_REGS* eQEPRegs,Uint16 lines, Uint16 polePairs);
00044 static inline void ConfigureEQEP(volatile struct EQEP_REGS* eQEPRegs,
00045 void(*interruptFCN)(void), Uint32 qUPRD, PCRM pcrm, Uint32 qPOSMAX);
00046 void InitEQep1Gpio(void);
00047 void InitEQep2Gpio(void);
00048
00049
00050
00051
00052
00053 void ConfigureQEP1(void(*interruptFCN)(void), Uint16 qep_us, PCRM pcrm,
00054 Uint16 lines, Uint16 polePairs)
00055 {
00056 Uint16 PRRSC = 1;
00057
00058
00059
00060 EALLOW;
00061 SysCtrlRegs.PCLKCR1.bit.EQEP1ENCLK=1;
00062 EDIS;
00063
00064 InitEQep1Gpio();
00065 ConfigureEQEP(&EQep1Regs, interruptFCN, US2CLOCK(qep_us, PRRSC), pcrm,
00066 (lines << 2) -1);
00067
00068 StoreQEPConf(&qep1, &EQep1Regs, lines, polePairs);
00069 }
00070
00071
00072
00073 void ConfigureQEP2(void(*interruptFCN)(void), Uint16 qep_us, PCRM pcrm,
00074 Uint16 lines, Uint16 polePairs)
00075 {
00076 Uint16 PRRSC = 1;
00077
00078
00079
00080 EALLOW;
00081 SysCtrlRegs.PCLKCR1.bit.EQEP2ENCLK=1;
00082 EDIS;
00083
00084 InitEQep2Gpio();
00085 ConfigureEQEP(&EQep2Regs, interruptFCN, US2CLOCK(qep_us, PRRSC), pcrm,
00086 (lines << 2) -1);
00087
00088 StoreQEPConf(&qep2, &EQep2Regs, lines, polePairs);
00089 }
00090
00091
00092
00093
00094 static inline void StoreQEPConf(volatile struct QEP* qep,
00095 volatile struct EQEP_REGS* eQEPRegs,Uint16 lines, Uint16 polePairs)
00096 {
00097 qep->eQEPRegs = eQEPRegs;
00098 qep->lines = lines;
00099 qep->polePairs = polePairs;
00100 qep->lastPos = 0;
00101 qep->theta_mech = 0;
00102 qep->theta_elec = 0;
00103 qep->w_mech = 0;
00104 qep->w_elec = 0;
00105
00106
00107
00108
00109
00110 qep->lines2Hz=_IQdiv( _IQ(CpuInHz()/
00111 ( eQEPRegs->QUPRD*(1<<eQEPRegs->QCAPCTL.bit.CCPS) )),
00112 _IQ(lines) ) >> 2;
00113 }
00114
00115
00116
00117 static inline void ConfigureEQEP(volatile struct EQEP_REGS* eQEPRegs,
00118 void(*interruptFCN)(void),Uint32 qUPRD, PCRM pcrm, Uint32 qPOSMAX)
00119 {
00120 eQEPRegs->QDECCTL.bit.QSRC=00;
00121 eQEPRegs->QEPCTL.bit.FREE_SOFT=2;
00122 eQEPRegs->QCAPCTL.bit.CCPS=0;
00123 eQEPRegs->QUPRD = qUPRD;
00124 eQEPRegs->QEPCTL.bit.PCRM=pcrm;
00125 eQEPRegs->QEPCTL.bit.UTE=1;
00126 eQEPRegs->QCAPCTL.bit.UPPS=0;
00127 eQEPRegs->QEPCTL.bit.QCLM=1;
00128 eQEPRegs->QPOSCNT=0;
00129 eQEPRegs->QPOSMAX=qPOSMAX;
00130 if(interruptFCN != 0){
00131 EALLOW;
00132
00133 eQEPRegs->QCLR.bit.INT=1;
00134 eQEPRegs->QCLR.bit.UTO=1;
00135 eQEPRegs->QEINT.all=0;
00136 eQEPRegs->QEINT.bit.UTO=1;
00137 if (eQEPRegs == &EQep1Regs) {
00138 PieVectTable.EQEP1_INT = interruptFCN;
00139 EDIS;
00140 PieCtrlRegs.PIEIER5.bit.INTx1 = 1;
00141 IER |= M_INT5;
00142 }
00143 else {
00144 PieVectTable.EQEP2_INT = interruptFCN;
00145 EDIS;
00146 PieCtrlRegs.PIEIER5.bit.INTx2 = 1;
00147 IER |= M_INT5;
00148 }
00149 }
00150 }
00151
00152
00153
00154 void InitEQep1Gpio(void)
00155 {
00156 ConfigureGPIOPort(_GPIO20, GPIO_INPUT, PERPH_1, GPIO_PULL_EN, GPIO_LOW);
00157 ConfigureGPIOPort(_GPIO21, GPIO_INPUT, PERPH_1, GPIO_PULL_EN, GPIO_LOW);
00158 ConfigureGPIOPort(_GPIO23, GPIO_INPUT, PERPH_1, GPIO_PULL_EN, GPIO_LOW);
00159 }
00160
00161
00162
00163 void InitEQep2Gpio(void)
00164 {
00165 ConfigureGPIOPort(_GPIO24, GPIO_INPUT, PERPH_1, GPIO_PULL_EN, GPIO_LOW);
00166 ConfigureGPIOPort(_GPIO25, GPIO_INPUT, PERPH_1, GPIO_PULL_EN, GPIO_LOW);
00167 ConfigureGPIOPort(_GPIO26, GPIO_INPUT, PERPH_1, GPIO_PULL_EN, GPIO_LOW);
00168 }
00169
00170
00171
00172 void SwapDirection(volatile struct QEP *qep)
00173 {
00174 qep->eQEPRegs->QDECCTL.bit.SWAP = 1;
00175 }
00176
00177
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00183